#
# Copyright (C) 2024, Advanced Micro Devices, Inc. All rights reserved.
# SPDX-License-Identifier: X11
#

set WORKING_DIR [pwd]

cd $WORKING_DIR

set list_projs [get_projects -quiet]
if { $list_projs eq "" } {
   create_project project_mode ./ -part xcvc1902-vsva2197-2MP-e-S
   set_property board_part xilinx.com:vck190:part0:3.2 [current_project]
}

set_property PR_FLOW 1 [current_project] 

# start_gui

#####Read all sources for building the project#####

# Read the system BD that has only CIPS and DDR NOCs
source ../sources/bd/bd.tcl

# Sourcing neccessary files
source ../sources/ip/static/axis_MxN_vio.tcl
source ../sources/ip/static/axi_dbg_hub_0.tcl
source ../sources/ip/rm1/axi_dbg_hub_rm1.tcl
source ../sources/ip/rm1/axis_vio_pl_master_to_ddr_rm1.tcl
source ../sources/ip/rm1/perf_axi_tg_pl_master_to_ddr_rm1.tcl
source ../sources/ip/rm2/axi_dbg_hub_rm2.tcl
source ../sources/ip/rm2/axis_vio_pl_master_to_ddr_rm2.tcl
source ../sources/ip/rm2/perf_axi_tg_pl_master_to_ddr_rm2.tcl

# Set the addressing parameter on debug hub IP
set_property CONFIG.C_ADDR_OFFSET {0x20400000000} [get_ips axi_dbg_hub_rm1]
set_property CONFIG.C_ADDR_RANGE {0x200000} [get_ips axi_dbg_hub_rm1]

set_property CONFIG.C_ADDR_OFFSET {0x20400000000} [get_ips axi_dbg_hub_rm2]
set_property CONFIG.C_ADDR_RANGE {0x200000} [get_ips axi_dbg_hub_rm2]


# start_gui

# Read the RTL files that has XPM NMUs and NSUs instantiated along with traffic generators and BRAM 
add_files ../sources/rtl/static
add_files ../sources/rtl/rm1
add_files ../sources/rtl/rm2
set_property top design_1_wrapper [current_fileset]

# Read the simulation testbench files to sim_1 fileset only
add_files -fileset sim_1 ../sources/testbench

# Read the XDC files for creating NoC connection, setting its QoS settings and the aperture of XPM NSUs. 
set top_noc_constraints [import_files -fileset constrs_1 ../sources/xdc/static/noc_constraints.xdc]
import_files -fileset constrs_1 ../sources/xdc/static/waivers_drc.xdc
add_files -fileset constrs_1 ../sources/xdc/static/pblocks.xdc
add_files -fileset constrs_1 ../sources/xdc/static/waivers_drc.xdc

#####Set the USED_IN {synthesis_pre} for NoC constraints#####
set_property USED_IN {synthesis_pre} $top_noc_constraints


# Read the XDC files that has constraints for creating ILAs and for connecting them to debug hub in the design. This constraint is auto-generated by the tool based on "Set up Debug" flow.
import_files -fileset constrs_1 ../sources/xdc/static/design_1_wrapper_debug.xdc

create_partition_def -name P0 -module RP1
create_reconfig_module -name RP1_rm1 -partition_def [get_partition_defs P0 ] -define_from RP1 -define_from_file [get_files ../sources/rtl/rm1/RP1_rm1.v]
create_reconfig_module -name RP1_rm2 -partition_def [get_partition_defs P0 ] -top RP1

# RM1 HDL files
add_files ../sources/rtl/rm1 -of_objects [get_reconfig_modules RP1_rm1]
move_files [get_files perf_axi_tg_pl_master_to_ddr_rm1.xci] -of_objects [get_reconfig_modules RP1_rm1]
move_files [get_files axis_vio_pl_master_to_ddr_rm1.xci] -of_objects [get_reconfig_modules RP1_rm1]
move_files [get_files axi_dbg_hub_rm1.xci] -of_objects [get_reconfig_modules RP1_rm1]


# RM2 HDL files
add_files ../sources/rtl/rm2 -of_objects [get_reconfig_modules RP1_rm2]
move_files [get_files perf_axi_tg_pl_master_to_ddr_rm2.xci] -of_objects [get_reconfig_modules RP1_rm2]
move_files [get_files axis_vio_pl_master_to_ddr_rm2.xci] -of_objects [get_reconfig_modules RP1_rm2]
move_files [get_files axi_dbg_hub_rm2.xci] -of_objects [get_reconfig_modules RP1_rm2]

# RM1 constraints
set rm1_noc_constraints [add_files ../sources/xdc/rm1/noc_constraints_rm1.xdc -of_objects [get_reconfig_modules RP1_rm1]]
set_property USED_IN {synthesis_pre} $rm1_noc_constraints
add_files ../sources/xdc/rm1/rm1_debug_project_mode.xdc -of_objects [get_reconfig_modules RP1_rm1]
add_files ../sources/xdc/static/waivers_drc.xdc -of_objects [get_reconfig_modules RP1_rm1]

# RM2 constraints
set rm2_noc_constraints [add_files ../sources/xdc/rm2/noc_constraints_rm2.xdc -of_objects [get_reconfig_modules RP1_rm2]]
set_property USED_IN {synthesis_pre} $rm2_noc_constraints
add_files ../sources/xdc/rm2/rm2_debug_project_mode.xdc -of_objects [get_reconfig_modules RP1_rm2]
add_files ../sources/xdc/static/waivers_drc.xdc -of_objects [get_reconfig_modules RP1_rm2]

#####Generate all targets : XCI/BD######
generate_target {synthesis instantiation_template} [get_files {design_1.bd axi_dbg_hub_0.xci axis_MxN_vio.xci axis_vio_pl_master_to_ddr.xci perf_axi_tg_pl_master_to_ddr.xci}]

##Updating the sourcefile set 
update_compile_order -fileset sources_1

# start_gui

##### Validate the NoC to see the project level NoC endpoints and paths
# validate_noc

create_pr_configuration -name config_1 -partitions [list RP1_inst:RP1_rm1 ]
create_pr_configuration -name config_2 -partitions [list RP1_inst:RP1_rm2 ]
set_property PR_CONFIGURATION config_1 [get_runs impl_1]
create_run child_0_impl_1 -parent_run impl_1 -flow {Vivado Implementation 2024} -pr_config config_2

launch_runs impl_1 child_0_impl_1 -to_step write_device_image -jobs 6

wait_on_runs impl_1 child_0_impl_1

#start_gui
exit
